This application is based upon and claims priority from prior French Patent Application No. 99-09970, filed Jul. 30, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a device for controlling a translator-type high voltage selector switch.
2. Description of Related Art
Conventional non-volatile electrically programmable memories are programmed using a voltage with a level higher than the logic supply voltage Vcc of the integrated circuit. The level of this high programming voltage depends on the technology used for the integrated circuit. Typically, the high voltage is applied to an integrated circuit element (for example, applied to a row of a memory) using a high voltage selector switch, which is also known as a level translator. The selector switch receives a logic control signal and a high voltage input. Depending on the logic level (Vcc or zero) of the logic circuit signal, which in the case of a memory comes from a write control signal, either the ground or the high voltage input level is supplied to the output of the selector switch.
CMOS selector switches usually have two arms, and each arm has two series-connected transistors between the high voltage input and ground. The bottom transistors are N-type transistors and have their sources connected to ground. They are known as selector switch transistors because one of these transistors receives the selection-switching signal and the other receives the reverse selection-switching signal. These selection-switching signals are logic signals whose level is zero or Vcc. The top transistors are P-type transistors and have their sources connected to a node that receives the high voltage input. Each of the P-type transistors has its gate connected to the drain of the upper transistor of the other arm. They are also known as load transistors.
The selector switch operates as follows. Depending on the levels of the selection switching signals, there is always a selector switch N-type transistor in one arm that is off and a selector switch N-type transistor in the other arm that is on. The N-type transistor that is on draws its drain towards zero volts (the potential of its source), and the P-type transistor of the other arm, which has its gate connected to this drain, turns on. Therefore, the P-type transistor takes its own drain to the voltage of its source, which is the high voltage input level.
Thus, at each connection node of the drains of the N-type and P-type transistors of the same arm, there is either the ground level or the high voltage input level. Additionally, conventional selector switches usually have an intermediate stage between the stage of the top transistors and the stage of the bottom transistors. This intermediate stage includes one or more cascode-connected stages that enable the internal nodes of the selector switch to be limited to intermediate voltage levels so that no transistor of the selector switch receives any excessively high voltage at its terminals.
In some conventional selector switch circuits, all of the N-type or P-type transistors of the cascode stage are biased at their gate by the logic supply voltage Vcc. This bias limits the range of operation of the selector switch. In particular, the switching over of the selector switch to provide the high voltage input level at output can only be done when the level of the input is sufficiently high (i.e., higher than the logic supply voltage Vcc.
With thin-oxide MOS technologies, the switching operation of the selector switch under high voltage has harmful transient effects on the MOS transistors. Furthermore, if there is biasing of the gates of the cascode transistors at the logic supply voltage while there is a voltage dependent on the high voltage input at the drains and sources of the cascode transistors, there is no link between these two voltages. This can give rise to additional stresses if the difference between these two voltages becomes excessively high.
For these reasons, it is preferable to bias the gates of the cascode-connected transistors at a reference voltage that is produced from the high voltage input. This makes it is possible to control the voltage difference between this reference voltage and the other high voltage input because the former depends on the latter. Thus, better protection is provided. In the case of a cascode stage with N-type and P-type MOS transistors, the gates of the N-type transistors of the cascode stage are usually biased at a reference voltage Vrefn that is higher than the reference voltage Vrefp which biases the gate of the P-type transistors of the cascode stage. This makes it possible to reduce the lower switch-over limit of the selector switch.
An example of this type of cascode stage selector switch is shown in FIG. 1. As shown, the upper stage includes a P-type MOS transistor M1 in the first arm and another P-type MOS transistor M2 in the second arm. These transistors receive the high voltage input EHV at their source. The bottom stage includes an N-type MOS transistor M3 in the first arm and another N-type MOS transistor M4 in the second arm. These transistors have their source connected to ground GND. The cascode stage includes four MOS transistors: two P-type MOS transistors M5 and M6 (one in each arm beneath each upper transistor), and two N-type MOS transistors M7 and M8 (one in each arm above each lower transistor). The P-type MOS transistors M5 and M6 receive reference voltage Vrefp at their gate. The N-type MOS transistors M7 and M8 receive reference voltage Vrefn at their gate.
The output Vout of the selector switch is provided between the N-type and P-type cascode-connected transistors of one arm (i.e., at the drains of transistors M6 and M8). The gate of the lower transistor M3 of the first arm of the selector switch receives a selection switching logic signal IN and the gate of the lower transistor M4 of the second arm of the selector switch receives the reverse signal /IN. The circuit REF that generates the reference voltages Vrefn and Vrefp includes three MOS transistors M9, M10 and M11 series-connected between the high voltage Vpp and ground. The three transistors operate as resistors because each has its gate connected to its drain. In the exemplary circuit, thee transistors are P-type transistors. The reference voltages Vrefn and Vrefp are provided on the two sides of the middle transistor M10.
The cascode stage acts to limit the voltages experienced by the transistors to intermediate levels. Each P-type cascode transistor is biased so that it is always on. Thus, the source of the transistor, and hence the drain of the P-type load transistor to which it is connected, cannot go below Vrefpxe2x88x92Vtp (where Vtp is the threshold voltage of the P-type cascode transistor). Similarly, each N-type cascode transistor is biased so as to always remain on. Thus, each has its source, and therefore the drain of the switching transistor to which it is connected, cannot rise above Vrefnxe2x88x92Vtn (where Vtn is the threshold voltage of the N-type cascode transistor).
There will now be described a practical example in which the high voltage input of the selector switch is in the form of a pulse with a voltage build-up ramp as shown in curve 1 of FIG. 2. Thus, in this example, the voltage increases linearly from zero to its rated value Vpp (the slope of the increase may be linear, logarithmic, exponential, and so on). Curves 2 and 3 show the progression of the reference voltages Vrefn and Vrefp. These curves show that the reference voltages follow the voltage build-up of the high voltage input EHV.
The differences between each of the reference voltages and the level of the high voltage input EHV at the beginning of the ramp (i.e., at the low voltage values of the input EHV) do not allow the transistors of the cascode stage to be conductive. At these low values of the high voltage input, the selector switch therefore cannot get switched. In one practical example in which the circuit is supplied by a Vcc of 3.3 volts, the level of the high voltage input should at least be higher than 3.8 volts so that it can switch over.
The switching at high values of the input EHV (i.e., values higher than Vcc) has the effect of contributing to the production of hot electrons. The repetition of selection switching commands greatly increases the quantity of these hot electrons, and ultimately causes deterioration in the characteristics of the transistors of the selector switch. For these reasons, conventional selector switches can withstand only a limited number of selection-switching operations.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a device in which the selector switch will switch over at the low values of the high voltage input. Once the transistors have switched over, the level of the high voltage input can rise without causing any harm to the transistors.
One embodiment of the present invention provides a control device for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference voltage generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.